A novel temperature and disturbance insensitive DAC calibration method

This paper presents a new foreground DAC calibration method that is insensitive to temperature fluctuations and on-chip disturbances. In the proposed current cell, the same number of unit transistors is always used, guaranteeing matched response for all current cells. These transistors are divided in two groups: a fixed group and a configurable group. The unit transistors in the configurable group can be interchanged with additional redundant unit transistors, such that the mismatch errors of the configurable group compensate the mismatch errors of the fixed group. Together they generate the needed output current. Thus all current cells feature matched temperature coefficients and dynamic response. For an exemplary 6+6bits segmented current steering DAC, the expected 99% yield INL improves with almost 3 bits while using only 30% additional unit transistors

A wideband RF mixing-DAC achieving IMD<-82 dBc up to 1.9 GHz

This paper presents a highly linear wideband Mixing-DAC architecture. A current-steering DAC core and a mixer are co-integrated at a unit current-cell level. A 1 bit DAC output stage is cascoded by a 1 bit mixer to form the Mixing-DAC current cell. An array of such current cells and a system front-end construct the Mixing-DAC. The system front-end includes digital signal processing and data synchronization, global LO driver and sort-and-combine calibration hardware. To reach high linearity, various techniques are used: digital dither, self measurement and calibration of amplitude and timing errors, local advanced cascoding scheme, bleeding currents, segmentation and accurate scaling of the LSB binary current cells. The proposed approach is validated by a 65 nm CMOS test-chip of a dual 16 bit 2 GS/s 4 GHz Mixing-DAC with IMD<−82 dBc up to 1.9 GHz and output noise lower than –165 dBm/Hz

A novel timing-error based approach for high speed highly linear Mixing-DAC architectures

In current steering Mixing-DACs with local mixing, timing errors between the current cells is a major concern. This paper considers two types of random timing errors: delay and duty-cycle. Analysis shows that the Mixing-DAC is sensitive to delay errors, but much less sensitive to duty-cycle errors. For the required high spectral purity of future 4GHz multicarrier GSM (SFDRRBW =85dBc), the delay spread s(delay) should b

Systematic analysis of the impact of mixing locality on Mixing-DAC linearity for multicarrier GSM

In an RF transmitter, the function of the mixer and the DAC can be combined in a single block: the Mixing-DAC. For the generation of multicarrier GSM signals in a basestation, high dynamic linearity is required, i.e. SFDR>85dBc, at high output signal frequency, i.e. ƒout ˜ 4GHz. This represents a challenge which cannot be addressed efficiently by current available hardware or state-of-the-art published solutions. Mixing locality indicates if the mixing operation is executed locally in each DAC unit cell or globally on the combined DAC output signal. The mixing locality is identified as one of the most important aspects of the Mixing-DAC architecture with respect to linearity. Simulations of a current steering Mixing-DAC show that local mixing with a local output cascode can result in the highest linearity, i.e. IMD3<-88dBc at ƒout=4GHz

A novel timing-error based approach for high speed highly linear Mixing-DAC architectures Citation for published version (APA): A novel timing-error based approach for high speed highly linear Mixing-DAC architectures

• A submitted manuscript is the version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. People interested in the research are advised to contact the author for the final version of the publication, or visit the DOI to the publisher's website. • The final author version and the galley proof are versions of the publication after peer review. • The final published version features the final layout of the paper including the volume, issue and page numbers. Link to publication General rights Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights. • Users may download and print one copy of any publication from the public portal for the purpose of private study or research. • You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the public portal. If the publication is distributed under the terms of Article 25fa of the Dutch Copyright Act, indicated by the "Taverne" license above, please follow below link for the End User Agreement: www.tue.nl/taverne Take down policy If you believe that this document breaches copyright please contact us at: [email protected] providing details and we will investigate your claim. Abstract-In current steering Mixing-DACs with local mixing, timing errors between the current cells is a major concern. This paper considers two types of random timing errors: delay and duty-cycle. Analysis shows that the Mixing-DAC is sensitive to delay errors, but much less sensitive to duty-cycle errors. For the required high spectral purity of future 4GHz multicarrier GSM (SF DRRBW =85dBc), the delay spread σ(delay) should be <36fs. Therefore, only mixing in the output stage with a single LO driver can achieve the desired linearity. The presented analysis shows that the timing of the binary cells in the segmented converter is very important, especially in a back-off scenario. Simulations confirm that accurate capacitance scaling at the high-frequency nodes of the binary current cells is crucial. A new, back-off aware segmentation trade-off is proposed, which shows the impact of the SF DRRBW and backoff requirements on the segmentation choice. The proposed methods result in an optimal Mixing-DAC architecture, implemented in 65nm CMOS, with a simulated performance of SF DRRBW =86dBc at 4GHz output frequency and -16dB FS /tone output power (10dB back-off)

Classification for synthesis of high spectral purity current-steering mixing-DAC architectures

This paper proposes a classification of Mixing-DAC architectures, focusing on spectral purity. Based on literature research, analysis and simulations, the proposed classification shows the impact of architectural choices on the output spectral purity. To concretize the classification and validate the analysis, a number of specific Mixing-DAC architectures are synthesized, discussed and simulated. Given the proposed classification, a set of optimal architectural choices lead to a strong architecture candidate for achieving high spectral purity at high signal frequencies, i.e. SFDR > 80 dBc at fOUT = 4 GHz for current and future multicarrier GSM applications. The main characteristics of this architecture are: Cartesian signaling, local Gilbert-cell mixing and a fully differential implementation

A 8mW-RX/113mW-TX, Sub-GHz SoC with time-dithered PA ramping for LPWAN applications

\u3cp\u3eThis work presents a fully-integrated sub-GHz radio System on Chip (SoC) for Low-Power Wide-Area Networks (LPWAN) and Internet of Things (IoT) applications. The receiver (RX) achieves 77dB blocker rejection and -106dBm sensitivity at 50kbps. The transmitter (TX) features a Switched-Capacitor Power Amplifier (SCPA) that delivers 13.5dBm output power. To fulfil stringent Japanese emission regulation, a novel digitally time-dithered SCPA ramping technique is proposed. The presented RX and TX consume 8mW and 113mW, respectively, from a supply as low as 1.2V.\u3c/p\u3